FPGA101: FROM RECONFIGURABLE TO DOMAIN-SPECIFIC SYSTEMS

(Project laboratory|Informatic laboratory|Frontal teaching)

Docente responsabile

DAVIDE CONFICCONI

CCS proponenti

Ingegneria Informatica

CFU

2

Ore in presenza

22

N° max studenti

30

Parole chiave:

Accelerator Cards, Domain Specific Systems, Embedded SoCs, FPGAS

Tag

Aerospace, Computer science, Engineering, Software

Descrizione dell'iniziativa

Overview The course aims to introduce students to the field of adaptable, reconfigurable, and domain-specific systems based mainly on FPGAs, discussing the system architecture, the different design flows, and how to interact with them.   To cope with the ever-growing innovation pace and performance demand, novel systems must adapt and specialize to a particular class of computations in a flexible and adaptable manner, even at the hardware level after manufacturing. Therefore, adaptive domain-specific computing systems are a unique opportunity to deliver energy-efficient computations that guarantee flexibility and performance as their ubiquity grows in many fields.The course encompasses a methodological approach to the three most important system-level topics: understanding the system design, the hardware/software co-design flow, and the hardware/software interaction. Based on that, the course aims to let students understand how to solve different HW/SW co-design trade-offs at a different level: low-level EDA with Vivado and RTL, IP/component design with Vitis HLS, System on Chip (SoC) and PYNQ-based interaction, Accelerator Cards for Datacenter, and the novel AI Engine technology in the context of Versal and Ryzen AI heterogeneous systems with Riallto.  At the end of the course, students must carry on a teaching-like project to complete their course, agreed with the teacher.

Periodo di svolgimento

dal October 2024 a December 2024

Calendario

1. FPGA Tecnology and design flows - 1/10, Aula Beta, Ed. 24 - Groundfloor
2. Vivado - 8/10, Aula Beta, Ed. 24 - Groundfloor
3. HLS 1: computing e data path 15/10, Aula Beta, Ed. 24 - Groundfloor
4. HLS 2: interface and communication 17/10, Aula Beta, Ed. 24 - Groundfloor
5. Pynq Theory 22/10, Aula Beta, Ed. 24 - Groundfloor
6. Pynq Practice 24/10, Aula Bio1, Ed. 21 - II Floor
7. Vitis Theory 28/10, Aula Beta, Ed. 24 – Groundfloor
8. Vitis Practice 30/10, Aula Beta, Ed. 24 - Groundfloor
9. Versal Systems 05/11, Aula Bio1, Ed. 21 - II Floor
10. Riallto 07/11, Aula Beta, Ed. 24 - Groundfloor
11. Open Discussion 14/11, Aula 1A, Ed. 20 – First Floor
12. Q&A [ON DEMAND] 3/12, Aula 1A, Ed. 20 - First Floor 

Note

Beyond PiA Students willing to pursue more advanced hard skills in the FPGA and Adaptive Systems path can continue in the following semester in the context of the AMD Open Hardware design contest (http://www.openhw.eu/). The AMD Open Hardware, AOHW, is a design contest at the European level, born in 2014 and promoted by Xilinx (now AMD), and sees FPGAs at the centre of project development for adaptive systems by teams of up to 5 participants. As Politecnico di Milano, we have participated since 2016, and since then, we have arrived among the finalists several times. With this course, we want to allow all Politecnico's students to participate in this competition supported by domain experts and students who have already participated and won the AOHW. In this way, we aim to create a heterogeneous context where this feature will help develop innovative ideas that can then be carried out in various projects.